• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The present invention includes an exclusive logical sum gate 30 for exclusively ORing two pulse signals outputted from the microprocessor 10 which is reset when the power switch 20 is turned on so as to have a phase difference of 180 ° from each other; A timer 40 for triggering the pulse signal and outputting a predetermined pulse signal when one of the two pulse signals applied to the exclusive OR gate 30 is input; A buffer 50 for buffering the output signal of the timer 40; The pulse generator 60 detects a state of an output signal of the exclusive logic sum gate 30 and an output signal of the buffer 50 and outputs a predetermined pulse signal for automatically turning off and then on the power switch 20. It relates to a reset circuit of the microprocessor comprising a. In this circuit, the predetermined driving power supply Vcc is applied to the microprocessor 10 and at the same time the microprocessor 10 is reset to active low, and then the driving power supply Vcc is supplied to the predetermined terminal of the microprocessor 10. When the microprocessor 10 latches up as a noise component capable of exceeding or rapidly changing) is applied, the power switch 20 is driven by a predetermined pulse signal output from the pulse generator 60. By automatically turning off and on again, the microprocessor 10 is automatically reset.
    公开号:KR19990032802A
    申请号:KR1019970053954
    申请日:1997-10-21
    公开日:1999-05-15
    发明作者:임재섭
    申请人:전주범；대우전자 주식회사；
    IPC主号:
    专利说明:

    A reset circuit of a micro processor
    BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reset circuit of a microprocessor, and more particularly, to a microprocessor reset circuit for applying a reset signal to the microprocessor while power is supplied to the microprocessor.
    In general, the microprocessor in the form of a single chip used in a PC main body or a monitor has a predetermined driving power through the power input terminal Vcc as the power switch 20 is turned on, as shown in FIG. 1. When Vcc) is applied, a predetermined digital control signal is output to control the operation of each part of the PC main body or the monitor. In addition, the microprocessor 10 outputs a normal control signal only after a predetermined driving power Vcc is applied through the power input terminal Vcc and then a reset signal is applied through the reset terminal Reset. That is, even when a driving power supply Vcc is supplied to the microprocessor 10, the microprocessor 10 may not operate until a predetermined time elapses after a reset signal is applied to the reset terminal Reset terminal of the microprocessor 10. Output a normal control signal. At this time, the operation of resetting the microprocessor 10 is as follows.
    As the power switch 20 is turned on, the reset terminal of the microprocessor 10 is uncharged when the capacitor C1 shown in FIG. 1 is not charged when the driving power source Vcc is first input to the microprocessor 10. A reset signal of a "LOW" state is applied to (Reset), and accordingly, the microprocessor 10 is reset. In addition, if a predetermined time passes after the microprocessor 10 is reset, the capacitor C1 is charged to the driving power supply (Vcc) level, and a reset signal of a "HIGH" state is applied to the reset terminal Reset of the microprocessor 10. Is applied, and the reset signal in the " HIGH " state is applied and the microprocessor 10 outputs a normal control signal. That is, the microprocessor 10 is reset to the active low while the driving power supply (Vcc) is applied to the power supply terminal (Vcc).
    However, as shown in FIG. 1, the reset circuit 20 of the microprocessor 10 operating in the active low as described above is driven by the driving power supply Vcc to a predetermined terminal of the microprocessor 10. As a noise component capable of exceeding or rapidly changing is applied, a latch up phenomenon in which an abnormal current flows between the power supply terminal Vcc and the ground terminal GND of the microprocessor 10 occurs. When the microprocessor 10 malfunctions, it is troublesome to completely shut off the driving power supply Vcc in order to solve the problem. That is, there is a hassle to reset the microprocessor 10 by unplugging the power cord of the PC main body or the monitor from the power supply outlet and plugging it back in.
    Thus, in order to solve the above problems, the present invention, when the microprocessor is latched up after the microprocessor is reset, the power switch is automatically turned off and then on again, thereby automatically It is an object of the present invention to provide a reset circuit of a microprocessor that resets the memory.
    In order to achieve the above object, the present invention provides an exclusive logic sum gate for exclusively ORing two pulse signals outputted so as to have a phase difference of 180 ° from a microprocessor that is reset when the power switch is turned on; A timer for triggering the pulse signal and outputting a predetermined pulse signal when one of the two pulse signals applied to the exclusive OR gate is input; A buffer for buffering the output signal of the timer; And a pulse generator for detecting a state of an output signal of the exclusive logic gate and an output signal of the buffer and outputting a predetermined pulse signal for automatically turning off and then on the power switch.
    In the circuit according to the present invention configured as described above, a predetermined driving power supply (Vcc) is applied to the microprocessor and at the same time the microprocessor is reset to active low and then the driving power supply (Vcc) to a predetermined terminal of the microprocessor. When the microprocessor is latched up as a noise component capable of exceeding or rapidly changing) is applied, the power switch is automatically turned off by a predetermined pulse signal output from the pulse generator. By turning it on, the microprocessor is automatically reset.
    1 is a circuit diagram showing a conventional microprocessor reset circuit;
    2 is a circuit diagram showing a reset circuit of the microprocessor according to the present invention.
    * Description of the symbols for the main parts of the drawings *
    10: microprocessor 20: power switch
    30: Exclusive Orgate 40: Timer
    50: buffer 60: pulse generator
    C1: capacitor
    Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
    2 is a circuit diagram showing a reset circuit of the microprocessor according to the present invention.
    As shown in FIG. 2, the embodiment according to the present invention exclusively sums two pulse signals outputted from the microprocessor 10 which is reset when the power switch 20 is turned on so that a phase difference of 180 ° occurs. A gate 30; A timer 40 which triggers the pulse signal and outputs a predetermined pulse signal when one of the two pulse signals applied to the exclusive OR gate 30 is input; A buffer 50 for buffering the output signal of the timer 40; A pulse generator for detecting a state of the output signal of the exclusive logic gate 30 and the output signal of the buffer 50 to output a predetermined pulse signal for automatically turning off and then on the power switch 20 It consists of 60.
    The operation of the embodiment according to the present invention configured as described above is as follows.
    First, as the power switch 20 is turned on, if the capacitor C1 shown in FIG. 2 is not charged when the driving power source Vcc is first input to the microprocessor 10, the microprocessor 10 of the microprocessor 10 is turned off. A reset signal of a "LOW" state is applied to a reset terminal Reset, and accordingly, the microprocessor 10 is reset. In addition, if a predetermined time passes after the microprocessor 10 is reset, the capacitor C1 is charged to the driving power supply (Vcc) level, and a reset signal of a "HIGH" state is applied to the reset terminal Reset of the microprocessor 10. Is applied, and the reset signal in the " HIGH " state is applied and the microprocessor 10 outputs a normal control signal. That is, the microprocessor 10 is reset to the active low while the driving power supply (Vcc) is applied to the power supply terminal (Vcc). In addition, the microprocessor 10 resets and outputs a normal control signal, and simultaneously outputs two pulse signals having a phase difference of 180 ° from each other through terminal A and terminal B as shown in FIG.
    Therefore, if two pulse signals outputted through the A terminal and the B terminal are input to the exclusive logical sum gate 30 during the normal operation of the microprocessor 10, the phases of the input signals are 180 ° different from each other. Therefore, the exclusive OR gate 30 outputs a high level signal. As shown in FIG. 2, when the pulse signal output through the A terminal is applied to the timer 40, the timer 40 generates this pulse. The signal is triggered to output a predetermined pulse signal, which is buffered by the buffer 50.
    As such, when the exclusive logic sum gate 30 outputs a high level signal and the timer 40 triggers a pulse signal output through the terminal A, the pulse generator 60 outputs a predetermined pulse signal. The microprocessor 10 detects that the microprocessor 10 is operating normally. In this case, the microprocessor 10 does not output a predetermined pulse signal for turning the power switch 20 off and on again.
    However, when a noise component capable of exceeding or rapidly changing the driving power supply Vcc is applied to a predetermined terminal of the microprocessor 10 and the microprocessor 10 is latched up, the microprocessor ( 10) outputs two pulse signals having the same phase with a high level or a low level through the A and B terminals.
    Therefore, when the microprocessor 10 is latched up, when two pulse signals output through the A terminal and the B terminal are input to the exclusive logical sum gate 30, the phases of the input signals are mutually different. As the same, the exclusive OR gate 30 outputs a low level signal, and as shown in FIG. 2, a pulse signal having a constant output characteristic such as a high level or a low level output through the A terminal is output to the timer 40. Is applied, the timer 40 does not trigger this pulse signal and therefore outputs a low level signal, which is buffered by the buffer 50.
    As such, when both the exclusive OR 30 and the timer 40 output the low level signal, the pulse generator 60 detects that the microprocessor 10 is latched up. At this time, the power switch 20 is turned off and then outputs a predetermined pulse signal to turn on again, and the user can directly unplug the power cord of the PC main body or the monitor from the power supply outlet, and then plug it back in again. Reset the processor 10 automatically.
    As described above, according to the present invention, after the microprocessor is reset to active low, a noise component capable of exceeding or rapidly changing driving power Vcc is applied to a predetermined terminal of the microprocessor. When the microprocessor is latched up, the power switch is automatically turned off and on again by a predetermined pulse signal output from the pulse generator, thereby automatically resetting the microprocessor. Vcc) has the effect of eliminating the hassle of blocking completely.
    权利要求:
    Claims (1)
    [1" claim-type="Currently amended] An exclusive logic sum gate 30 for exclusively ORing two pulse signals outputted from the microprocessor 10 which is reset when the power switch 20 is turned on so as to have a phase difference of 180 ° from each other;
    A timer 40 which triggers the pulse signal and outputs a predetermined pulse signal when one of the two pulse signals applied to the exclusive OR gate 30 is input;
    A buffer 50 for buffering the output signal of the timer 40;
    A pulse generator for detecting a state of the output signal of the exclusive logic gate 30 and the output signal of the buffer 50 to output a predetermined pulse signal for automatically turning off and then on the power switch 20 Reset circuit of a microprocessor, characterized in that it comprises a (60).
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    同族专利:
    公开号 | 公开日
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1997-10-21|Application filed by 전주범, 대우전자 주식회사
    1997-10-21|Priority to KR1019970053954A
    1999-05-15|Publication of KR19990032802A
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019970053954A|KR19990032802A|1997-10-21|1997-10-21|Reset circuit of microprocessor|
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